About the speaker
Dr. Yervent Zorian a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business School, University of Pennsylvania.
Abstract
With increasing system complexity and stringent runtime requirements in high-performance computing and autonomous vehicles, reliable and secure operation of electronics in safety-critical applications are still a major challenge. This talk will focus on optimizing silicon health by using advanced solutions throughout the silicon life cycle stages, from design stage, to bring up, to volume production and in-field operation. The advanced solutions for silicon lifecycle management (SLM) to be discussed will include various sensors and monitors embedded in different levels of the design stack, access mechanisms and standards for such on-chip and in-system sensor network, as well as data analytics on the edge and in the cloud for fleet monitoring.
This is a very timely topic for both industry and academia, and spans in various parts of the silicon ecosystem from technology, foundry, design, EDA, test solutions, verification and debug, to in-field deployment, as well as IP, SoC and system integration, EDA, and cloud sectors. It also needs the use of data analytics at chip, system and cloud as well as the standards and interaction of various DfX infrastructures.