Fundamentals of ESD and Latch-up device physics and implications for optimum ESD Design

The seminar will be given by Gianluca Boselli, Manager of the Corporate ESD and Spice Modeling Teams, Texas Instruments, Dallas, TX, as part of the course "Industrial Trends in Electronics M"

  • Date: 06 June 2022 from 16:00 to 17:00

  • Event location: Room 2.6, viale Risorgimento 2, Bologna, and online on Microsoft Teams

  • Access Details: Free admission

About the speaker

Dr. Gianluca Boselli (Master in EE at the University of Parma-Italy, 1996, PhD at the University of Twente-The Netherlands, 2001) is with Texas Instruments, Inc., Dallas, Texas, since 2001. He is currently the manager of the corporate ESD and Spice Modeling Teams. He authored many papers about ESD and latch-up, which were presented at major conferences/journals. Dr. Boselli has been the recipient of multiple best paper awards on behalf of Microelectronics Reliability Journal and EOS/ESD Symposium. He served multiple times as sub-committee chair for technical program committees (TPC) of EOS/ESD Symposium, IEDM, IRPS, IEW, and ESREF. Dr. Boselli has served as TPC chair at the EOS/ESD Symposium 2006, vice-general chair at the EOS/ESD Symposium 2007, and general chair at the EOS/ESD Symposium 2008. He is currently a member of the board of directors of EOS/ESD Association, where he served as President in 2018-2019. He is the recipient of the ESDA Outstanding Contribution Award. Dr. Boselli is an IEEE senior member and holds over thirty patents with several pending. Dr. Boselli serves in the editorial board of the IEEE Transactions on Device and Materials Reliability (T-DMR).

Abstract

This tutorial focuses on the physics of basic components under high-injection conditions, typical of ESD events. Parasitic components are analyzed as well. The components’ behavior is primarily reported for bulk technologies, down to 32nm. The understanding of basic components' physics under high-injection conditions is the fundamental building block to any ESD designer/engineer. It allows the engineer to optimize the component’s layout to maximize its performance (failure current vs Area). This, in turn, will enable the creation of optimum ESD Cells layout. Additionally, the extraction of the critical parameters of any component in a given design, will allow the engineer to generate the ESD Design Window (i.e. the I-V area where the ESD Cell is expected to operate to be efficient, robust, and transparent to normal operating conditions). This is the critical piece of information needed to successfully integrate effective ESD cells into any design.