Seminars: Distributed Machine Learning for Large-scale IoT Systems - Test and emerging memories

The seminars will be given by Dr. Rob Aitken, Research & Development Fellow, ARM, as part of the course "Trends in Electronics M."

  • Date: 04 May 2018

  • Event location: Room 5.2, School of Engineering and Architecture, viale Risorgimento 2, Bologna

Contact Name:

Contact Phone: + 39 051 209 3013

About the speaker

Rob Aitken is an ARM Fellow responsible for technology direction at ARM Research. He works on a variety of topics including distributed systems, low power design, technology roadmapping, and next generation memories. He has worked on 15+ Moore’s law nodes and has published over 80 technical papers.

Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

 

Abstract

1. Distributed Machine Learning for Large-scale IoT Systems

The Internet of Things vision promises systems where huge numbers of sensors gather data and machine learning algorithms in the cloud process and make sense of it. While such solutions sound desirable and simple in theory, their practical implementation is complicated. In particular, there are multiple communication bottlenecks between the sensors and the cloud, as well as large amounts of unexploited compute capability along the way. This talk looks at some of the issues involved and explores promising avenues for future innovation.

2. Test and emerging memories

As device scaling slows down, memories are among the hardest hit circuits. Bit cell dimensions push the limits of design rules, and dense structures make achieving high yields difficult, even with the regularity of memory structures. The workhorse memories of the last twenty years, SRAM, DRAM and NAND flash are all facing significant challenges going forward. While the dominant technologies have struggled, some radically new memory technologies have been proposed to take their place.

This talk looks at what these technologies are and where they fit within the memory hierarchy, but also looks at their test implications: What failure modes are likely? How can a resistive crosspoint be tested? What redundancy and repair methods make sense and what yield issues can they cover? Answering these questions is key to commercial success for emerging memories, but the answers are different enough that some of our intuition about memory test will need replacing in order to reflect a new reality.