The Road to Gate-All-Around and Its Impact on Analog Design

About the speaker

Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Angstrom-era CMOS technologies. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received his B.A.Sc. with highest honors from the University of British Columbia, and M.S. and Ph.D. from Stanford. Upon graduating, he spent several years in CMOS process integration. Since 2001, he has worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. He has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves in the VLSI Symposium committee and as SSCS Chapters Chair. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents.

Abstract

CMOS scaling maintains economic relevance with 3nm FinFET SoCs already in the marketplace for a year now and 2nm gate-all-around SoCs well into risk production. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we start with a brief history of transistor evolution to motivate the migration from planar to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the FinFET CMOS nodes, highlighting the resulting device technology characteristics and challenges impacting design. To address the growing effort required for analog/mixed-signal design closure, we cover design strategies including density-friendly layout and template-based analog cells and touch on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling. We conclude with a discussion of transistor architectures on the horizon.