Incontro Seminar: Scan Compression Techniques to Improve Test Time and Quality
16 - 17 maggio 2016
The seminar will be given by Dr. Juergen Alt, Intel Corporation, as part of the courses "Trends in Electronics M" and "Design for Testability and Reliability of Integrated Circuits M.".
- In presenza : School of Engineering and Architecture, viale Risorgimento 2, Bologna
- In inglese
Programma
Contact Name: Prof. Cecilia Metra
Contact Phone: +39 051 2093013
Event schedule
- Monday, May 16 2016, 9-11, room 5.6
- Tuesday, May 17 2016, 9-12, room 2.7A
About the speaker
Juergen Alt is with Intel Corporation based in Munich, Germany. He is responsible for Design-for-Test Methodology for Intel’s mobile business. Juergen is working in Design & Test, EDA-Software and Reliability since more than 20 years. In 1995 he received a PhD from University of Hannover, Germany and started his industrial career the same year with Siemens Semiconductors (later Infineon).
Abstract
The world of Microelectronics is characterized by decreasing feature sizes and by this faces a continuous increase of complexity. The development of scan compression techniques was a significant innovative step to address increasing complexity to test logic parts of microelectronic products. This seminar guides you through the basics of test and Design-for-Test. After a summary of scan test and Automated Test Pattern Generation (ATPG) focus is on scan compression as one of the most advanced Design-for-Test techniques. Different implementations as well as the theoretical limits of compression are discussed. Insights into practical implementation for industrial designs are given.