Seminario: BTI-aware Energy-efficient Designs: Aging Comes with Benefits!

Il seminario sarà tenuto dal Dr. Daniele Rossi, University of Southampton, UK, nell'ambito del corso "Sistemi Elettronici ad Alta Affidabilità M".

  • Data: 28 ottobre 2015 dalle 09:00 alle 11:00

  • Luogo: Aula 2.7a, Scuola di Ingegneria e Architettura, viale Risorgimento 2, Bologna

Contatto di riferimento:

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Abstract

Power consumption has become a major issue for modern ICs. Power density is reaching the limits of what packaging and cooling can support, and static power due to leakage current is increasing to the point where, in some current designs, it can be nearly as large as dynamic power, if proper countermeasures are not taken. Along with power issues, electronic systems at nano-scale are increasingly suffering from reliability reduction due to BTI aging. It causes performance degradation in logic, which eventually may exceed circuit time margin, as well as static noise margin and soft error resiliency reduction in memories. BTI-induced reliability degradation can be further exacerbated by the adoption of energy efficient/low power design techniques.

In this talk, I will show that BTI aging, together with its detrimental effect for circuit reliability, presents considerable benefits in terms of static power reduction, making low power design more efficient and effective over time. Then, I will present some design strategies for reliable energy efficient/low power designs able to harvest the leverage offered by BTI aging benefits.

About the speaker

Dr Daniele Rossi received the Laurea degree in electronic engineering and the Ph.D. degree in electronic engineering and computer science from the University of Bologna, Italy, in 2001 and 2005, respectively. Then he joined the department of Department of Electrical, Electronic and Information Engineering at the same university, working on several projects addressing the development of fault tolerant design and test techniques for electronic circuits and systems. Since 2014, he is with the ECS department of the University of Southampton as Senior Research Fellow. His current research interests include fault modelling and design for reliability and test, focusing on energy-efficient and reliable digital design, robust design for soft error and aging resiliency, and high quality test for low power systems.