Contatto di riferimento: Prof. Cecilia Metra
Recapito telefonico per contatti: +39 051 20 93013
Abstract
Multicore SoC architectures are built connecting via a Network on Chip a set of processors, GPUs, hardware accelerators, I/O interfaces to one or more DDR memory controllers. They represent an effective solution to cope with the today performance power tradeoff requirements in consumer, networking and mobile markets. Unfortunately, their use in markets domains, such as automotive, healthcare, avionics, is very limited due to the fact that they are built maximizing the overall DDR focusing on ACET instead of WCET. In this presentation we are going to illustrate the DREAMS architecture that has been defined within the DREAMS FP7 Project.
The DREAMS architecture template is a cross-domain architecture and design tools for networked complex systems where application subsystems of different criticality, executing on networked multi-core chips, are supported. Then we show how the DREAMS architecture provides several platform services, which separate the application functionality from the underlying platform technology in order to reduce design complexity and to facilitate the achievement of temporal and spatial partitioning, real-time support, reliability, security and energy-efficiency. We conclude the presentation addressing the associated methodology to validate the integration of applications with different timing models and different safety assurance levels.
About the speaker
Marcello Coppola is the Technical Director of STMicroelectronics, overseeing the contents of STMicroelectronics' Research Portfolio in several aspects of System-on-Chip, with particular emphasis in Network-on-Chip, multi-core architecture, cloud computing and programming models. He's co-author and/or co-editor of different books, 24 patents and more than 100 papers/presentations in international conferences. He is serving as program and organizing member in numerous top international conferences and workshops currently drives the concrete realization of the advanced R&D for the communication architecture, verification and modeling inside STMicroelectronics.