Seminario: Trends in Computer Architecture

Il seminario sarà tenuto dal Prof. Jean-Luc Gaudiot, President Elect della IEEE Computer Society, University of California, Irvine, USA, nell'ambito dei corsi "Design for Testability and Reliability of Integrated Circuits M" e "Trends in Electronics M".

Data: dal 21 marzo 2016 al 22 marzo 2016
Luogo: Aula Magna Scuola di Ingegneria e Architettura, viale Risorgimento 2, Bologna

Contatto di riferimento: Prof. Cecilia Metra

Recapito telefonico per contatti: +39 051 2093013

Seminar schedule

Monday, March 21, 9-11
Tuesday, March 22, 9-12

About the speaker

Jean-Luc Gaudiot received the Diplôme d'Ingénieur from ESIEE, Paris, France in 1976 and the M.S. and Ph.D. degrees in Computer Science from UCLA in 1977 and 1982, respectively. He is currently Professor in the Electrical Engineering and Computer Science Department at UC, Irvine. Prior to joining UCI in 2002, he was Professor of Electrical Engineering at the University of Southern California since 1982.

His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 250 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as a number of industrial companies.

He has served the community in various positions and was just elected to the presidency of the IEEE Computer Society for 2017.

Abstract

Computer systems have undergone a fundamental transformation recently, from single-core processors to devices with increasingly higher core counts within a single chip. The semi-conductor industry now faces the infamous power and utilization walls. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, etc., can eliminate the energy overheads of general-purpose homogeneous cores. However, with future technological challenges pointing in the direction of on-chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware.

As a case in point, the core count per chip continues to increase dramatically while the available on-chip memory per core is only getting marginally bigger. Thus, data locality, already a must-have in high-performance computing, will become even more critical as memory technology progresses. In turn, this makes it crucial that new execution models be developed to better exploit the trends of future heterogeneous computing in many-core chips.

In this series of lectures, we will demonstrate the cross-cutting, cross-layer approach we have proposed to address the challenges posed by future heterogeneous many-core chips. We will enumerate some important problems we have identified and describe some possible solutions; among those, the invention of new approaches to exploit the parallelism offered by large scale parallel processors, the careful consideration of power considerations in mobile and embedded systems, the crucial need to adapt design techniques to new technologies, etc. Finally, we will look into our crystal ball and envision a future where Moore’s law rules no longer.